According to a typical architecture of the prior art, an electrically erasable and programmable memory of the EEPROM or FLASH type, a part of which is schematically represented in FIGS. 1 and 2 for example, includes memory cells Cij organized in a memory plane according to a matrix of n×m cells disposed in n rows (or lines) and m columns, each being situated at the intersection of a word line and of a bit line. In such a memory, each cell Cij, more particularly visible in FIG. 2, can contain an item of information. Accordingly, each cell comprises a storage transistor TM which comprises a specific zone designed to trap or free an electric charge, representative of the binary item of information, which can be modified electrically via electrodes of the cell during, for example, a write operation or an erase operation. Such a cell Cij moreover comprises a second transistor, called an access or selection transistor TS, which participates in the memory cell control operations.
More precisely, the EEPROM memory part represented by FIG. 1, for example, comprises two columns and four rows, with which are associated four word lines of 8 bits WLi to WLi+3. In each of these rows, the memory part in fact comprises eight bit lines (respectively BL0 to BL7 and BL8 to BL15) linked to eight memory cells. In this example represented, these eight cells disposed at each intersection of a column and of a row thus form a memory octet or word.
FIG. 2 more precisely represents such a memory octet. Each memory cell of this octet, such as the highlighted cell C10, comprises a storage transistor TM and a selection transistor TS as discussed above. The selection transistor has its gate G connected to the word line WLi, its drain D connected to a bit line BL0 and its source S connected to the drain D of the storage transistor TM. This storage transistor has its common source LS connected to a source line LS and its control gate G connected to a gate control line CGL0. It is therefore noted that each memory cell Cij therefore comprises four electrodes linked to the remainder of the memory architecture.
The production of a semiconducting component such as a non-volatile memory as described hereinabove requires the fabrication of the various cells, considered individually, as simply as possible. Thereafter, it is also necessary to allow the production of the electrical connections of the four electrodes of each cell so as to form an electrical component comprising several cells, as in the case of the EEPROM memory. In onboard memories fabricated by a method of the CMOS type, making it possible to integrate these memories into integrated circuits, the natural method of fabrication rests upon various conventional steps, including a special isotropic etching making it possible to remove a part of the polycrystalline silicon spacers used.
A cell of the prior art, represented in FIG. 3, comprises a first selection transistor accessible through notably a selection gate 3 formed by a polysilicon film. This selection gate 3 is separated from the substrate 1, of silicon wafer type, by a dielectric insulating layer 2, an oxide film. The cell moreover comprises a storage transistor, comprising a charge trapping zone 4. This charge trapping zone 4 is disposed in part laterally, between the selection gate 3 and a control gate 5. It is also separated from these two gates by insulating zones. Finally, the cell comprises laterally a source zone 6 and a drain zone 7. Lateral spacers 8 laterally cover the central zone overlaid on the substrate and disposed between the source and drain zones.
FIGS. 4 to 12 schematically illustrate cross-sectional views of a cell according to several steps of a method for fabricating such a cell. FIG. 4 represents a method starting situation in which a first dielectric material layer 2 has been disposed on a substrate 1, and then a second polysilicon layer 3. FIG. 5 represents the result obtained after a step of lateral etching of the structure of FIG. 4. Thereafter, a layer 4 is disposed on the upper contour of the whole of this structure, to achieve the result represented in FIG. 6. This layer 4 can take the form of an assembly of layers allowing the trapping of electric charges. Thereafter, a polysilicon deposition, followed by an etching step, makes it possible to produce spacer type zones 5, 5′ on the two flanks of the previously produced gate, to obtain the result of FIG. 7. The right zone or spacer in this FIG. 7 is intended to form the control gate 5 of the memory cell.
The method then comprises an additional step which includes removing the zone 5′ formed on the left of FIG. 7, symmetrically with the right part of the structure, as well as the dielectric layer 4 on this left part above the substrate 1, to obtain the result of FIG. 8. Accordingly, a photomasking step makes it possible to etch in an isotropic manner the zone 5′ to be eliminated. As a supplement, the dielectric layer 4 which rests horizontally on the substrate 1 and which overhangs the control gate 5 is likewise discarded, to allow the future silicidation of the gates and active zones. Finally, the result obtained is represented in FIG. 9.
Thereafter, lateral spacers 8 are formed, according to a conventional procedure employing CMOS technology, to obtain the result represented by FIG. 10, and then the upper surface of this assembly is treated to form silicide conducting layers 9 at the level of the future electrodes of the memory cell, as represented in FIG. 11, and on which are finally added contacts 10, to achieve the final form of the structure represented by FIG. 12. Note, this method also includes the formation of the source 6 and drain 7 zones by various known doping processes, not described here.
The result obtained represented by FIG. 12 therefore includes a cell comprising two transistors and four electrodes 10 respectively linked to the source zone 6, drain zone 7, selection gate zone 3 and control gate zone 5. This method of fabrication exhibits the drawback of being complex, difficult to integrate into CMOS logic, without adding numerous steps, and of making it difficult to produce the electrical links between the electrodes of the various cells in a semiconducting component of the non-volatile memory type.
Thus, there exists a need to improve the structure of such semiconducting components, notably to simplify their method of fabrication so as to reduce their cost, while achieving reliable, efficacious, and compact components.